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publication release date: may 17, 2007 - 1 - revision 1.4 isd4002 series single-chip, multiple-messages voice record/playback devices 120-, 150-, 180-, and 240-second duration
isd4002 series - 2 - 1. general description the isd4002 chipcorder ? series provides high-quality, 3-volt, single-chip record/playback solutions for 2- to 4-minute messaging applications ideally for cellular phones and other portable products. the cmos-based devices include an on-chip oscillator, anti-aliasing filter, smoothing filter, automute ? feature, audio amplifier, and high density multileve l flash memory array. the isd4002 series is designed to be used in a microprocessor- or micr ocontroller-based system. address and control are accomplished through a serial peripheral interface (spi) or microwire serial interface to minimize pin count. recordings are stored into the on-chip flash me mory cells, providing zero-power message storage. this unique single-chip solution utilizes winbond? s patented multilevel storage technology. voice and audio signals are directly stored onto memory array in their natural form, providing high-quality voice reproduction.
isd4002 series publication release date: may 17, 2007 - 3 - revision 1.4 2. features ? single-chip voice record/playback solution ? single 3 volt supply ? low-power consumption ? operating current: - i cc_play = 15 ma (typical) - i cc_rec = 25 ma (typical) ? standby current: - i cc_standby = 1 a (typical) ? single-chip durations of 120, 150, 180, and 240 seconds ? high-quality, natural voice/audio reproduction ? automute feature provides background noise attenuation ? no algorithm development required ? micorcontroller spi or microwire? serial interface ? fully addressable to handle multiple messages ? non-volatile message storage ? 100k record cycles (typical) ? 100-year message retention (typical) ? on-chip clock source ? power consumption controlled by spi or microwire control register ? available in die, pdip, soic and tsop ? packaged type: lead-free ? temperature: - commercial (die): 0c to +50c - commercial (packaged units): 0c to +70c - industrial (packaged units): -40c to +85c
isd4002 series - 4 - 3. block diagram internal clock timing sampling clock 960k cell nonvolatile multilevel storage array analog transceivers decoders power conditioning 5-pole active antialiasing filter 5-pole active smoothing filter amp audout v cca v ssa v ssa v ssa xclk amp ana in- ana in+ am cap device control sclk ss mosi miso int rac automute tm feature v ssd v ccd
isd4002 series publication release date: may 17, 2007 - 5 - revision 1.4 4. table of contents 1. general description .................................................................................................................. 2 2. features ......................................................................................................................................... 3 3. block diagram .............................................................................................................................. 4 4. table of contents ...................................................................................................................... 5 5. pin configuration ....................................................................................................................... 6 6. pin description ............................................................................................................................. 7 7. functional description .......................................................................................................... 12 7.1. detailed description .................................................................................................................... 12 7.2. serial peripheral interface (spi) description .............................................................................. 13 7.2.1. opcodes ........................................................................................................................... 14 7.2.2. spi diagrams ....................................................................................................................... 15 7.2.3. spi control and output registers ........................................................................................ 16 8. timing diagrams .......................................................................................................................... 18 9. absolute maximum ratings .................................................................................................... 20 9.1. operating conditions .................................................................................................................. 21 10. electrical characteristics ............................................................................................... 22 10.1. parameters for packaged parts .............................................................................................. 22 10.2. parameters for die .................................................................................................................. 25 10.3. spi ac parameters .................................................................................................................. 26 11. typical application circuit ................................................................................................. 27 12. packaging and die information ......................................................................................... 30 12.1. 28-lead 300-mil plastic small outline ic (soic) ..................................................................... 30 12.2. 28-lead 600-mil plastic dual inline package (pdip) ............................................................... 31 12.3. 28-lead 8x13.4mm plastic thin small outline package (tsop) type 1 - iqc ...................... 32 12.4. 28-lead 8x13.4mm plastic thin small outline package (tsop) type 1 ................................ 33 12.5. die information ......................................................................................................................... 34 13. ordering information ........................................................................................................... 36 14. version history ....................................................................................................................... 37
isd4002 series - 6 - 5. pin configuration soic / pdip ss mosi miso v ssd nc nc nc nc nc nc v ssa v ssa aud out am cap v ccd xclk int rac v ssa nc nc nc nc v cca ana in+ ana in- nc sclk isd4002 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 isd4002 nc nc v cca ana in+ ana in- nc am cap nc aud out v ssa v ssa nc nc nc v ssa rac nc nc int xclk v ccd sclk ss mosi miso v ssd nc nc tsop 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15
isd4002 series publication release date: may 17, 2007 - 7 - revision 1.4 6. pin description pin no. pin name soic / pdip tsop function ss 1 9 slave select : this input, when low, will select the isd4002 device. mosi 2 10 master out slave in : this is the serial input to the isd4002 device when it is confi gured as slave. the master microcontroller places data on the mosi line one half-cycle before the rising edge of sclk for clocking into the device. miso 3 11 master in slave out : this is the serial output (open drain) of the isd4002 device. this output goes into a high- impedance state if the dev ice is not selected. v ssa / v ssd 11, 12, 23 / 4 1, 17, 18 / 12 ground : the isd4002 series utilizes separate analog and digital ground busses. the analog ground (v ssa ) pins should be tied together as close as possible and connected through a low-impedance path to power supply ground. the digital ground (v ssd ) pin should be connected through a separate low-impedance path to power supply ground. these ground paths should be large enough to ensure that the impedance between the v ssa pins and the v ssd pin is less than 3 ? . the backside of the die is connected to v ss through the substrate. for chip-on-board design, the die attach area must be connected to v ss or left floating. nc 5-10, 15, 19-22 3, 4, 13- 16, 19, 21, 23, 27, 28 not connected aud out [ ] 1 13 20 audio output : this pin provides an audio output of the stored data and is recommended be ac coupled. it is capable of driving a 5 k ? impedance r ext . [ ] 1 the aud out pin is always at 1.2 volts when the dev ice is powered up. when in playback, the output buffer connected to this pin can dr ive a load as small as 5 k ? . when in record, a resistor connects aud out to the internal 1.2-volt analog ground supply. this resistor is approximately 850 k ? , but will vary somewhat according to the sample rate of the device. this relatively hi gh impedance allows this pin to be connected to an audio bus without loading it down.
isd4002 series - 8 - pin no. pin name soic / pdip tsop function am cap 14 22 automute? feature : the automute feature only applies for playback operation and helps to minimize noise (with 6 db of attenuation) when there is no signal (i.e. during periods of silence). a 1 f capacitor to ground is recommended to connect to the am cap pin. this capacitor becomes a part of an internal peak detector which senses the signal amplitude. this peak level is compared to an internally set threshold to determine the automute trip point. for large signals, the automute attenuation is set to 0 db automatically but 6 db of attenuation occurs for silence. the 1 f capacitor also affects the rate at which the automute feature changes with the signal amplitude (or the attack time). the automute feature can be disabled by connecting the am cap pin directly to v cca .. ana in- 16 24 inverting analog input : this pin transfers the signal into the device during recording via differential-input mode. in this differential-input mode, a 16 mvp-p maximum input signal should be capacitively coupled to ana in- for optimal signal quality, as shown in figure 1: ana in modes. this capacitor value should be equal to that used on ana in+ pin. the input impedance at ana in- is normally 56 k ? . in the single-ended mode, ana in- should be capacitively coupled to v ssa through a capacitor equal to that used on the ana in+ pin. ana in+ 17 25 non-inverting analog input : this pin is the non-inverting analog input that transfers t he signal to the device for recording. the analog input amplifier can be driven single ended or differentially. in the single-ended input mode, a 32 mvp-p (peak-to-peak) maximum signal should be capacitively connected to this pin for optimal signal quality. the external capacitor associated with ana in+ together with the 3 k ? input impedance are selected to give cutoff at the low frequency end of the voice passband. in the differential-input mode, the maximum input signal at ana in+ should be 16 mvp-p capacitively coupled for optimal signal quality. the circuit connections for the two modes are shown in figure 1.
isd4002 series publication release date: may 17, 2007 - 9 - revision 1.4 pin no. pin name soic / pdip tsop function v cca / v ccd 18 / 27 26 / 7 supply voltage : to minimize noises, the analog and digital circuits in the isd4002 dev ices use separate power busses. these +3v busses are brought out to separate pins and should be tied together as close to the supply as possible. in addition, these supplies should be decoupled as close to the package as possible. rac 24 2 row address clock : this is an open drain output that provides the signal of a row with a 200 ms period for 8 khz sampling frequency. (this represents a single row of memory) this signal stays high for 175 ms and stays low for 25 ms when it reaches the end of a row. the rac pin stays high fo r 109.37 sec and stays low for 15.63 sec in message cueing mode (see message cueing section for detailed description). refer to the ac parameters table for rac timing information at other sample rates. when a record command is first initiated, the rac pin remains high for an extra t racl period. this is due to the need of loading the internal sample and hold circuits in the device. this pin can be used for message management techniques. a pull-up resistor is required to connect to other device. int 25 5 interrupt : this is an open drain output pin. this pin goes low and stays low when an overflow (ovf) or end of message (eom) marker is detected. each operation that ends with an eom or ovf will generate an interrupt. the interrupt will be cleared the next time an spi cycle is initiated. the interrupt status can also be read by an r int instruction. a pull-up resistor is required to connect to other device. overflow flag (ovf) ? the overflow flag indicates that the end of memory has been reached during a record or playback operation. end of message (eom) ? the end of message flag is set only during playback operation when an eom is found. there are eight eom flag position options per row.
isd4002 series - 10 - pin no. pin name soic / pdip tsop function xclk 26 6 external clock input : the isd4002 series is configured at the factory with an internal sampling clock frequency centered to 1 percent of specification. the frequency is then maintained to a variation of 2.25 percent over the entire commercial temperature and operating voltage ranges. the internal clock has a ?6/+4 percent tolerance over the industrial temperature and voltage ranges. a regulated power supply is recommended for industrial temperature range parts. if great er precision is required, the device can be clocked through the xclk pin as follows: part number sample rate required clock isd4002-120 8.0 khz 1024 khz isd4002-150 6.4 khz 819.2 khz isd4002-180 5.3 khz 682.7 khz isd4002-240 4.0 khz 512 khz these recommended clock rates should not be varied because the anti-aliasing and smoothing filters are fixed. otherwise, aliasing problems can occur if the sample rate differs from the one recommended. the duty cycle on the input clock is not critical, as the clock is immediately divided by two. if the xclk is not used, this input must be connected to ground. sclk 28 8 serial clock : this is the input clock to the isd4002 device. it is generated by the master device (typically microcontoller) and is used to synchronize the data transfer in and out of the device through the mosi and miso lines, respectively. data is latched into the isd4002 on the rising edge of sclk and shifted out of the device on the falling edge of sclk.
isd4002 series publication release date: may 17, 2007 - 11 - revision 1.4 32m vp-p signal 0.1 f 0.1 f ana in+ ana in- 3k 3k 53k 53k 1.2v to filter internal to the device - + single-ended input mode 16m vp-p input signal 0.1 f 0.1 f ana in+ ana in- 3k 3k 53k 53k 1.2v to filter internal to the device - + differential input mode 16m vp-p 180 input signal figure 1: isd4002 series ana in modes rac t rac (200 ms) 25 ms t racl figure 2: rac timing waveform during normal operation (example of 8khz sampling rate)
isd4002 series - 12 - 7. functional description 7.1. d etailed d escription audio quality the winbond?s isd4002 chipcorder ? series is offered at 8.0, 6.4, 5.3 and 4.0 khz sampling frequencies, allowing the user a choice of speec h quality options. increasing the sampling frequency will produce better sound quality, but affects duration. please refer to table 1: product summary for details. analog speech samples are stored directly into on-ch ip non-volatile memory without the digitization and compression associated with other solutions. direct analog storage provides higher quality reproduction of voice, music, tones, and sound effects than other solid-state solutions. duration the isd4002 series is a single-chip solution with 120, 150, 180, and 240 seconds duration. table 1: product summary of isd4002 series part number duration (seconds) sample rate (khz) typical filter pass band (khz) * isd4002-120 120 8.0 3.4 isd4002-150 150 6.4 2.7 isd4002-180 180 5.3 2.3 isd4002-240 240 4.0 1.7 * this is the ?3db point. this parameter is not che cked during production testing and may vary due to process variations and other factors. theref ore, the customer should not rely upon this value for testing purposes. flash storage the isd4002 series utilizes on-chip flash memo ry, providing zero-power message storage. the message is retained for up to 100 years typically without power. in addition, the device can be re- recorded typically over 100,000 times. memory architecture the isd4002 series contains a total of 960k flash memory cells, which is organized as 600 rows of 1,600 cells each.
isd4002 series publication release date: may 17, 2007 - 13 - revision 1.4 microcontroller interface a four-wire (sclk, mosi, miso & ss ) spi interface is provided for controlling and addressing functions. the isd4002 is configured to operate as a peripheral slave device, with a microcontroller- based spi bus interface. read and write operations are controlled through this spi interface. an interrupt signal ( int ) and internal read only status regist er are provided for handshake purposes. programming the isd4002 series is also ideal for playback-only applications, where single- or multiple-messages playback is controlled through the spi port. once the desired message configuration is created, duplicates can easily be generated via a programmer. 7.2. s erial p eripheral i nterface (spi) d escription the isd4002 series operates via spi serial interface with the following protocol. first, the data transfer protocol assumes that the microcontroller?s spi shift registers are clocked on the falling edge of the sclk. however, for t he isd4002, the protocols are as follows: 1. all serial data transfers begin with the falling edge of ss pin. 2. ss is held low during all serial communications and held high between instructions. 3. data is clocked in on the rising edge of t he sclk signal and clocked out on the falling edge of the sclk signal, with lsb first. 4. playback and record operations are initiat ed when the device is enabled by asserting the ss pin low, shifting in an opcode and an address data to the isd4002 device (refer to the opcode summary in the following page). 5. the opcodes contain <11 address bits> and <5 control bits>. 6. each operation that ends with an eom or ov erflow will generate an interrupt. the interrupt will be cleared the next time a spi cycle is initiated. 7. as interrupt data is shifted out of the miso pin, control and address data are simultaneously shifted into the mosi pin. care should be taken such that the data shifted in is compatible with current system operation. because it is possible to read an interrupt data and start a new operation within the same spi cycle. 8. an operation begins with the run bit set and ends with the run bit reset. 9. all operations begin after the rising edge of ss .
isd4002 series - 14 - 7.2.1. opcodes the available opcodes are summarized as follows: table 2: opcode summary opcodes instructions address (11 bits) control bits (5 bits) c0 c1 c2 c3 c4 descriptions powerup 0 0 1 0 0 power-up: device will be ready for an operation after t pud . setplay 0 0 1 1 1 initiates playback from address . play 0 1 1 1 1 playback from the current address (until eom or ovf). setrec 0 0 1 0 1 initiates a record operation from address . rec 0 1 1 0 1 records from current address until ovf is reached or stop command is sent. setmc 1 0 1 1 1 initiates message cueing (mc) from address . mc [ ] 2 1 1 1 1 1 performs a message cueing from current location. proceeds to the end of message (eom) or enters ovf condition if no more messages are present. stop 0 1 1 x 0 stops the current operation. stoppwrdn x 1 0 x 0 stops the current operation and enters into standby (power-down) mode. rint [ ] 3 0 1 1 x 0 read interrupt status bits: overflow and eom. notes: c0 = message cueing c1 = ignore address bit c2 = master power control c3 = record or playback operation c4 = enable or disable an operation [ ] 2 message cueing can be selected only at the beginning of a playback operation. [ ] 3 as the interrupt data is shifted out of the isd4002, control and address dat a are being shifted in. care should be taken such that the data shifted in is compatible with current system oper ation. it is possible to read interrupt data and start a new operation at the same time. see figures 5 - 8 for references.
isd4002 series publication release date: may 17, 2007 - 15 - revision 1.4 7.2.2. spi diagrams row counter output shift register input shift register select logic mosi miso a0-a9 p0-p9 (loaded to row counter only if iab = 0) ovf eom figure 3: spi interface simplified block diagram the following diagram describes the spi port and the control bits associated with it. ovf eom p0 p1 p2 p3 p4 p5 p6 p7 p8 p9 x 0 0 0 a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 0 c0 c1 c2 c3 c4 miso mosi message cueing (mc) ignore address bit (iab) power up (pu) play/record (p/r) run lsb msb figure 4: spi port
isd4002 series - 16 - 7.2.3. spi control and output registers the spi control register provides control of indi vidual device functions such as play, record, message cueing, power-up and power-down, start and stop operations, and ignore address pointers. table 3: spi control registers control bit control register bit device function c0 mc = = 1 0 message cueing function enable message cueing disable message cueing c1 iab [ ] 4 = = 1 0 ignore address bit ignore input address register (a0-a9) use the input address register (a0-a9) c2 pu = = 1 0 power up bit power-up power-down c3 p/ r = = 1 0 playback or record bit play record c4 run = = 1 0 enable or disable an operation start stop address bits a0-a9 input address register table 4: spi output registers output bits description ovf overflow eom end-of-message p0-p9 output of the row pointer register [ ] 4 when iab (ignore address bit) is set to 0, a playback or record operation starts from address (a0-a9). for consecutive playback or record, iab should be changed to a 1 before the end of t hat row (see rac timing). otherwise the isd4002 will repeat the operation from the same row addre ss. for memory management, the row address clock (rac) signal and iab can be us ed to move around the memory segments.
isd4002 series publication release date: may 17, 2007 - 17 - revision 1.4 message cueing message cueing (mc) allows the user to skip thr ough messages, without knowing the actual physical location of the messages. it will stop when an eom ma rker is reached. then, the internal address counter will point to the next message. also, it will enter into ovf condition when it reaches the end of memory. in this mode, the messages are ski pped 1,600 times faster than the normal playback mode. power-up sequence the isd4002 will be ready for an operation after power-up command is sent and followed by the t pud timing (25 ms for 8 khz sampling rate). refer to the ac timing table for other t pud values with respect to different sampling rates. the following sequences are recommended for optimized record and playback operations. record mode 1. send powerup command. 2. wait t pud (power-up delay). 3. send powerup command. 4. wait 2 x t pud (power-up delay). 5. a). send setrec command with address xx, or b). send rec command (recording from current location). 6. send stop command to stop recording. 7. wait t stop/pause. for 5.a), the device will start recording at address xx and will generate an interrupt when an overflow (end of memory array) is reached, if no stop co mmand is sent before that. then, it will automatic stop recording operation. playback mode 1. send powerup command 2. wait t pud (power-up delay) 3. a). send setplay command with address xx, or b). send play command (playback from current location). 4. a). send stop command to halt the playback operation, or b). wait for playback operation to stop autom atically, when an eom or ovf is reached. 5. wait t stop/pause. for 3.a), the device will start playback at addre ss xx and it will generate an interrupt when an eom or ovf is reached. it will then stop playback operation.
isd4002 series - 18 - 8. timing diagrams t ssh t ssmin t sckhi t sss t dis t dih t scklow t pd t pd t df (tristate) lsb ss sclk mosi miso figure 5: timing diagram ss sclk mosi miso a8 a9 x c0 c1 c2 c3 c4 ovf eom p0 p1 p2 p3 p4 p5 lsb lsb figure 6: 8-bit command format
isd4002 series publication release date: may 17, 2007 - 19 - revision 1.4 ss sclk mosi miso lsb lsb a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 x c0 c1 c2 c3 c4 xxxx p9 p8 p7 p6 p5p4p3p2p1p0 eom ovf figure 7: 16-bit command format ss sclk mosi miso ana in ana out data play/ recor d st data op (rec) (play) t stop/pause t stop/pause figure 8: playback/re cord and stop cycle
isd4002 series - 20 - 9. absolute maximum ratings table 5: absolute maximum ratings (packaged parts) conditions values junction temperature 150oc storage temperature range -65oc to +150oc voltage applied to any pin (v ss ?0.3v) to (v cc +0.3v) voltage applied to any pin (input current limited to 20ma) (v ss ?1.0v) to (v cc +1.0v) voltage applied to mosi, sclk, and ss pins (input current limited to 20ma) (v ss ?1.0v) to 5.5v lead temperature (soldering ? 10 seconds) 300oc v cc ? v ss -0.3v to +7.0v table 6: absolute maximum ratings (die) conditions values junction temperature 150oc storage temperature range -65oc to +150oc voltage applied to any pad (v ss ?0.3v) to (v cc +0.3v) voltage applied to any pad (input current limited to 20 ma) (v ss ?1.0v) to (v cc +1.0v) voltage applied to mosi, sclk, and ss pins (input current limited to 20ma) (v ss ?1.0v) to 5.5v v cc ? v ss -0.3v to +7.0v note: stresses above those listed may cause permanent damage to the device. ex posure to the absolute maximum ratings may affect device reliability and perform ance. functional operation is not implied at these conditions.
isd4002 series publication release date: may 17, 2007 - 21 - revision 1.4 9.1. o perating c onditions table 7: operating conditions (packaged parts) condition value commercial operating temperature range (case temperature) 0oc to +70oc industrial operating temperature (cas e temperature) -40oc to +85oc supply voltage (v cc ) [1] +2.7v to +3.3v ground voltage (v ss ) [2] 0v table 8: operating conditions (die) condition value commercial operating temperature range 0oc to +50oc supply voltage (v cc ) [1] +2.7v to +3.3v ground voltage (v ss ) [2] 0v [1] v cc = v cca = v ccd [2] v ss = v ssa = v ssd
isd4002 series - 22 - 10. electrical characteristics 10.1. p arameters f or p ackaged p arts table 9: dc parameters parameter symbol min [2] typ [1] max [2] units conditions input low voltage v il v cc x 0.2 v input high voltage v ih v cc x 0.8 v output low voltage v ol 0.4 v i ol = 10 a rac, int output low voltage v ol1 0.4 v i ol = 1 ma output high voltage v oh v cc x 0.4 v i oh = -10 a v cc current (operating) - playback - record i cc 15 25 30 40 ma ma r ext = [3] r ext = [3] v cc current (standby) i sb 1 10 a [3] [4] input leakage current i il 1 a miso tristate current i hz 1 10 a output load impedance r ext 5 k ? ana in+ input resistance r ana in+ 2.2 3.0 3.8 k ? ana in- input resistance r ana in- 40 56 71 k ? ana in+ or ana in- to aud out gain a arp 20 23 26 db 1 khz sinewave input [5] notes: [1] typical values @ t a = 25c and v cc = 3.0v. [2] all min/max limits are guaranteed by winbond via electronical testing or characterization. not all specifications are 100 percent tested. [3] v cca and v ccd connected together. [4] ss = v cca = v ccd , xclk = mosi = v ssa = v ssa and all other pins floating. [5] measured with automute feature disabled.
isd4002 series publication release date: may 17, 2007 - 23 - revision 1.4 table 10: ac parameters (packaged parts) characteristic symbol min [2] typ [1] max [2] units conditions sampling frequency isd4002-120 isd4002-150 isd4002-180 isd4002-240 f s 8.0 6.4 5.3 4.0 khz khz khz khz [5] [5] [5] [5] filter pass band isd4002-120 isd4002-150 isd4002-180 isd4002-240 f cf 3.4 2.7 2.3 1.7 khz khz khz khz 3 db roll-off point [3][7] 3 db roll-off point [3][7] 3 db roll-off point [3][7] 3 db roll-off point [3][7] record duration isd4002-120 isd4002-150 isd4002-180 isd4002-240 t rec 120 150 180 240 sec sec sec sec [6] [6] [6] [6] playback duration isd4002-120 isd4002-150 isd4002-180 isd4002-240 t play 120 150 180 240 sec sec sec sec [6] [6] [6] [6] power-up delay isd4002-120 isd4002-150 isd4002-180 isd4002-240 t pud 25 31.25 37.5 50 msec msec msec msec stop or pause in record or play isd4002-120 isd4002-150 isd4002-180 isd4002-240 t stop or t pause 50 62.5 75 100 msec msec msec msec rac clock period isd4002-120 isd4002-150 isd4002-180 isd4002-240 t rac 200 250 300 400 msec msec msec msec [10] [10] [10] [10] rac clock low time isd4002-120 isd4002-150 isd4002-180 isd4002-240 t racl 25 31.25 37.5 50 msec msec msec msec rac clock period in message cueing mode isd4002-120 isd4002-150 isd4002-180 isd4002-240 t racm 125 156.3 187.5 250 sec sec sec sec rac clock low time in message cueing mode isd4002-120 isd4002-150 isd4002-180 isd4002-240 t racml 15.63 19.53 23.44 31.25 sec sec sec sec total harmonic distortion thd 1 2 % @ 1 khz sinewave ana in input voltage v in 32 mv peak-to-peak [4] [8] [9]
isd4002 series - 24 - notes: [1] typical values @ t a = 25c, v cc = 3.0v and timing measurement at 50%. [2] all min/max limits are guaranteed by winbond via electrical testing or characterization. not all specifications are 100 percent tested. [3] low-frequency cutoff depends upon the value of ex ternal capacitors (see pin descriptions) [4] single-ended input mode. in the differential input mode, v in maximum for ana in+ and ana in- is 16 mvp-p. [5] sampling frequency can vary as much as 2.25 percent over the comme rcial temperature and voltage ranges, and ?6/+4 percent over the industrial tem perature and voltage ranges. fo r greater stability, an external clock can be utilized (see pin descriptions) [6] playback and record duration can vary as much as 2.25 percent over the co mmercial temperature and voltage ranges, and ?6/+4 percent over the industrial temperatur e and voltage ranges. for greater stability, an external clock c an be utilized (see pin descriptions) [7] filter specification applies to t he antialiasing filter and t he smoothing filter. theref ore, from input to output, expect a 6 db drop by nature of passing through both filters. [8] the typical output voltage will be approximately 450 mvp-p with v in at 32 mvp-p. [9] for optimal signal quality, this maximum limit is recommended. [10] when a record command is sent, t rac = t rac + t racl on the first row address.
isd4002 series publication release date: may 17, 2007 - 25 - revision 1.4 10.2. p arameters f or d ie table 11: dc parameters parameters [6] symbol min [2] typ [1] max [2] units conditions v cc current (operating) -playback -record i cc 15 25 30 40 ma ma r ext = [3] r ext = [3] v cc current (standby) i sb 1 10 a [3] [4] total harmonic distortion thd 1 2 % @ 1 khz sinewave ana in+ or ana in- to aud out gain a arp 20 23 26 db [5] notes: [1] typical values @ t a = 25c and v cc = 3.0v. [2] all min/max limits are guaranteed by winbond via electrical testing or characterization. not all specifications are 100 percent tested. [3] v cca and v ccd connected together. [4] ss = v cca = v ccd , xclk = mosi = v ssa = v ssa and all other pins floating. [5] measured with automute feature disabled. [6] the test coverage for die is limited to room temperat ure testing. the test conditions may differ from that of packaged parts.
isd4002 series - 26 - 10.3. spi ac p arameters table 12: ac parameters [1] parameter symbol min typ max units conditions setup time t sss 500 nsec ss ss hold time t ssh 500 nsec data in setup time t dis 200 nsec data in hold time t dih 200 nsec output delay t pd 500 nsec output delay to highz [2] t df 500 nsec ss high t ssmin 1 sec sclk high time t sckhi 400 nsec sclk low time t scklow 400 nsec clk frequency f 0 1,000 khz notes: [1] typical values @ t a = 25 c, v cc = 3.0v and timing measurement at 50%. [2] tri-state test condition. miso v cc 6.32k 10.91k 50pf (includes scope and fixture capacitance)
isd4002 series publication release date: may 17, 2007 - 27 - revision 1.4 11. typical application circuit these application examples are for illustration purposes only. winbond makes no representation or warranty that such application will be suitable for production. make sure all bypass capacitors are as close as possible to the package. 68hc705c8p isd4002 15-30 pf c9 15-25 pf c8 10 k r7 47 k r6 47 k r5 39 38 1 2 37 35 11 10 9 8 7 6 5 4 19 18 17 16 15 14 13 12 21 22 23 24 25 26 27 28 34 33 32 31 30 29 3 2 28 1 16 17 24 25 26 14 13 11 12 23 18 4 27 13 14 5 6 7 3 2 16 9 8 4 1 12 15 10 11 c11 0.1 f c12 0.1 f c5 1 f c4 1 f c3 0.22 f c2 0.22 f c1 47 f v cc r1 10k r2 1m r3 100 r4 100k pot line out ext speaker c6 1 f c7 .1 f j4 3 2 4 5 1 3 2 1 3 4 5 1 j1 u 3 u 1 u 2 lm4860m ocs1 ocs2 reset irq tcap tcmp pa0 pa1 pa2 pa3 pa4 pa5 pa6 pa7 pd7 pb0 pb1 pb2 pb3 pb4 pb5 pb6 pb7 pc0 pc1 pc2 pc3 pc4 pc5 pc6 pc7 pd0/rdi pd1/td0 pd2/miso pd3/mosi pd4/sck pd5/ss miso mosi sclk ss ana in- ana in+ rac int xclk am cap v ccd v ssd v cca v ssa v ssa v ssa aud out -in +in bypass hp-in1 hp-in2 hpsense shutdown gain-out v01 v02 v dd gnd gnd gnd gnd gnd pdip / soic figure 9: application example using spi
isd4002 series - 28 - pic16c62a isd4002 r7 8 19 1 20 9 11 21 7 14 16 15 3 2 28 1 16 17 24 25 26 14 13 11 12 23 18 4 27 13 14 5 6 7 3 2 16 9 8 4 1 12 15 10 11 c9 0.1 f c8 0.1 f c5 1 f c4 1 f c3 0.22 f c2 0.22 f c1 47 f v cc r1 10k r2 1m r3 100 r4 100k pot line out ext speaker c6 1 f c7 .1 f j4 3 2 4 5 1 3 2 1 3 4 5 1 j1 u 3 u 1 u 2 lm4860m v ss v ss mclr v dd osc1 rc0 rb0 rc4 rc5 rc3 ra5 miso mosi sclk ss ana in- ana in+ rac int xclk am cap v ccd v ssd v cca v ssa v ssa v ssa aud out -in +in bypass hp-in1 hp-in2 hpsense shutdown gain-out v01 v02 v dd gnd gnd gnd gnd gnd pdip / soic c10 4.7 k r6 4.7 k r5 figure 10: application example using microwire
isd4002 series publication release date: may 17, 2007 - 29 - revision 1.4 cop 820c isd4002 r7 23 24 6 5 25 19 20 21 22 3 2 28 1 16 17 24 25 26 14 13 11 12 23 18 4 27 13 14 5 6 7 3 2 16 9 8 4 1 12 15 10 11 c9 0.1 f c8 0.1 f c5 1 f c4 1 f c3 0.22 f c2 0.22 f c1 47 f v cc r1 10k r2 1m r3 100 r4 100k pot line out ext speaker c6 1 f c7 .1 f j4 3 2 4 5 1 3 2 1 3 4 5 1 j1 u 3 u 1 u 2 lm4860m gnd reset v cc cli d3 d2 d1 d0 miso mosi sclk ss ana in- ana in+ rac int xclk am cap v ccd v ssd v cca v ssa v ssa v ssa aud out -in +in bypas s hp-in1 hp-in2 hpsense shutdown gain-out v01 v02 v dd gnd gnd gnd gnd gnd pdip / soic c10 4.7 k r6 4.7 k r5 10 11 12 13 3.3 k 82 pf 7 8 9 10 g3 g2 g1 int si sk g7 so l7 l6 l5 l4 l3 l2 l1 l0 11 12 13 14 15 16 17 18 1 4 2 3 26 27 28 figure 11: application example using spi port on microcontroller
isd4002 series - 30 - 12. packaging and die information 12.1. 28-l ead 300-m il p lastic s mall o utline ic (soic) 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 45 67 8 910 11 12 13 14 a d e f b g c h inches millimeters min nom max min nom max a 0.701 0.706 0.711 17.81 17.93 18.06 b 0.097 0.101 0.104 2.46 2.56 2.64 c 0.292 0.296 0.299 7.42 7.52 7.59 d 0.005 0.009 0.0115 0.127 0.22 0.29 e 0.014 0.016 0.019 0.35 0.41 0.48 f 0.050 1.27 g 0.400 0.406 0.410 10.16 10.31 10.41 h 0.024 0.032 0.040 0.61 0.81 1.02 note: lead coplanarity to be within 0.004 inches.
isd4002 series publication release date: may 17, 2007 - 31 - revision 1.4 12.2. 28-l ead 600-m il p lastic d ual i nline p ackage (pdip) inches millimeters min nom max min nom max a 1.445 1.450 1.455 36.70 36.83 36.96 b1 0.150 3.81 b2 0.065 0.070 0.075 1.65 1.78 1.91 c1 0.600 0.625 15.24 15.88 c2 0.530 0.540 0.550 13.46 13.72 13.97 d 0.19 4.83 d1 0.015 0.38 e 0.125 0.135 3.18 3.43 f 0.015 0.018 0.022 0.38 0.46 0.56 g 0.055 0.060 0.065 1.40 1.52 1.62 h 0.100 2.54 j 0.008 0.010 0.012 0.20 0.25 0.30 s 0.070 0.075 0.080 1.78 1.91 2.03 q 0 15 0 15
isd4002 series - 32 - 12.3. 28-l ead 8 x 13.4 mm p lastic t hin s mall o utline p ackage (tsop) t ype 1 - iqc a a a 2 1 l l 1 y e h d d b e c min. dimension in inches nom. max. min. nom. max. symbol 1.20 0.05 0.15 1.05 1.00 0.95 0.17 0.10 11.70 7.90 13.20 0.50 0.00 0 0.20 0.27 0.15 0.21 11.80 11.90 8.00 8.10 13.40 13.60 0.55 0.60 0.70 0.80 0.10 35 0.047 0.006 0.041 0.040 0.035 0.007 0.008 0.011 0.004 0.006 0.008 0.461 0.465 0.469 0.311 0.315 0.319 0.520 0.528 0.536 0.022 0.020 0.024 0.028 0.031 0.000 0.004 035 0.002 a a b c d e e l l y 1 1 2 a h d dimension in mm
isd4002 series publication release date: may 17, 2007 - 33 - revision 1.4 12.4. 28-l ead 8 x 13.4 mm p lastic t hin s mall o utline p ackage (tsop) t ype 1 5 6 7 8 9 10 11 12 13 14 2 3 4 15 16 17 18 19 20 21 22 23 24 25 26 27 28 a b g f c d e h j i a b g c f e h j 4 8 10 1 2 3 5 6 7 9 11 12 13 14 18 20 24 17 16 15 19 21 22 23 25 26 27 28 inches millimeters min nom max min nom max a 0.520 0.528 0.535 13.20 13.40 13.60 b 0.461 0.465 0.469 11.70 11.80 11.90 c 0.311 0.315 0.319 7.90 8.00 8.10 d 0.002 0.006 0.05 0.15 e 0.007 0.009 0.011 0.17 0.22 0.27 f 0.0217 0.55 g 0.037 0.039 0.041 0.95 1.00 1.05 h 0 3 6 0 3 6 i 0.020 0.022 0.028 0.50 0.55 0.70 j 0.004 0.008 0.10 0.21 note: lead coplanarity to be within 0.004 inches.
isd4002 series - 34 - 12.5. d ie i nformation isd4002 series isd4002 miso mosi ss v ccd sclk int rac v ssa v ssd v ssd v ccd xclk v cca [3] ana in+ am cap aud out v ssa [3] v ssa ana in- v ssa [3] v cca [3] o die dimensions [1] x: 166.6 1 mils y: 222.5 1 mils o die thickness [2] 11.5 0.5 mils o pad opening single pad opening: 90 x 90 m double pad opening: 180 x 90 m notes: [1] the backside of die is internally connected to v ss . it must not be connected to any other potential or damage may occur. [2] die thickness is subject to change, please contac t winbond as this thickness may change in the future. [3] double bond is recommended if treated as one single pad.
isd4002 series publication release date: may 17, 2007 - 35 - revision 1.4 isd4002 s eries p ad c oordinations (with respect to die center) pad pad description x axis (m) y axis (m) v ssa analog ground 1885.7 2606.7 rac row address clock 1483.8 2606.7 int interrupt 794.8 2606.7 xclk external clock input 564.8 2606.7 v ccd digital power supply 384.9 2606.7 v ccd digital power supply 169.5 2606.7 sclk slave clock -14.7 2606.7 ss slave select -198.1 2606.7 mosi master out slave in -1063.7 2606.7 miso master in slave out -1325.6 2606.7 v ssd digital ground -1665.3 2606.7 v ssd digital ground -1836.9 2606.7 v ssa [1] analog ground -1943.1 -2607.4 v ssa [1] analog ground -1853.1 -2607.4 v ssa analog ground -1599.9 -2607.4 aud out audio output 281.9 -2607.4 am cap automute 577.3 -2607.4 ana in- inverting analog input 1449.3 -2607.4 ana in+ noninverting analog input 1603.5 -2607.4 v cca [1] analog power supply 1853.5 -2607.4 v cca [1] analog power supply 1943.8 -2607.4 note: [1] double bond recommended if treated as one pad.
isd4002 series - 36 - 13. ordering information isd4002- product family : product series : isd4000 family 02 = second series (2-4 min) duration : 120 = 120 seconds 150 = 150 seconds 180 = 180 seconds 240 = 240 seconds special temperature field : blank = commercial package (0c to + 70c) or commercial die (0c to + 50c) i = industrial (-40c to + 85c) packaged units / die : x = die p = 28-lead 600-mil plastic dual inline package (pdip) s = 28-lead 300-mil plastic small outline package (soic) e = 28-lead 8x13.4mm plastic thin small outline packa g e ( tsop ) t yp e 1 package type: y = lead-free when ordering the devices, please refer to the fo llowing valid ordering numbers and contact the local winbond sales representatives for availability. duration 120 seconds 150 seconds 180 seconds 240 seconds type package part # order # part # order # part # order # part # order # die isd4002-120x i4212x isd4002-150x i4215x isd4002-180x i4218x isd4002-240x i4224x pdip ISD4002-120PY i4212py isd4002-150py i4215py isd4002-180py i4218py isd4002-240py i4224py isd4002-120sy i4212sy isd4002-150sy i4215sy isd4002-180sy i4218sy isd4002-240sy i4224sy soic isd4002-120syi i4212syi isd4002-150syi i4215syi isd4002-180syi i4218syi isd4002-240syi i4224syi isd4002-120ey i4212ey isd4002-150ey i4215ey isd4002-180ey i4218ey isd4002-240ey i4224ey lead-free tsop isd4002-120eyi i4212eyi isd4002-150eyi i4215eyi isd4002-180eyi i4218eyi isd4002-240eyi i4224eyi for the latest product information, access winbond worldwide website at http://www.winbond-usa.com
isd4002 series publication release date: may 17, 2007 - 37 - revision 1.4 14. version history version date description 0 june 2000 initial version 1 sep. 2003 reformat the document. add note for typical filter pass band. add memory architecture description. remove all csp info. revise rac timing parameter for mc. revise automute: playback only. revise spi, opcodes sections, record & playback steps. rename t raclo to t racl . revise a arp parameter. revise dc & ac parameters tables for die. revise die information: pad opening and (x,y) coordinates. figures 9-11: revise v cca and v ccd pin #. 1.1 mar. 2005 add lead-free parts. revise am cap name in block diagram. update table no. for ac parameter. revise the ordering information. revise disclaim section. 1.2 apr. 2005 standardize disclaim section. 1.3 oct. 2005 revise packaging information. 1.4 may 2007 remove the leaded package option remove the extended temperature option update the external clock description revise ordering information section
isd4002 series - 38 - copyright ? 2005, winbond electronics corporation. all rights reserved. chipcorder ? and isd ? are trademarks of winbond electronics corporation. superflash ? is the trademark of silicon storage technology, inc. all other trademarks are properties of their respective owners. this datasheet and any future addendum to this datasheet is(are) the complete and controlling isd ? chipcorder ? product specifications. in the event any inconsistencies exist between the information in this and other product documentation, or in the event that other product documentat ion contains information in addition to the information in this, the information contained herein supersedes and governs su ch other information in its entirety. this datasheet is subject to change without notice. information contained in this isd ? chipcorder ? datasheet supersedes all data fo r the isd chipcorder products published by isd ? prior to august, 1998. the 100-year retention and 100k record cycle projections are based upon accelerated reliability tests, as published in the winbond reliability report, and are nei ther warranted nor guaranteed by wi nbond. this product incorporates superflash ? . application examples and alternative uses of any integrated circuit contained in this publication are for illustration only and winbond makes no representation or warranty that such applications shall be suitable for the use specified. the contents of this document are pr ovided ?as is?, and winbond assumes no liability whatsoever and disclaims any express or implied warranty of merchant ability, fitness for a particular purpose or infringement of any intellectual property. in no event, shall winbond be liable for any damages w hatsoever (including, wit hout limitation, damages for loss of profits, business interruption, loss of information) arising out of the use of or inability to use the contents of this documents, even if winbond has been advised of the possibility of such damages. the contents of this document are provided only as a guide for the applications of winbond products. winbond makes no representation or warranties with respect to the accuracy or completeness of the c ontents of this publication and reserves the right to discontinue or make changes to specif ications and product descriptions at any time without notice. no license, whether express or implied, to any intellectual property or other right of winbond or others is granted by this publication. except as set forth in winbond's standard terms and conditions of sale, winbond assumes no liability whatsoever and disclaims any express or implied warrant y of merchantability, fitness for a particular purpose or infringement of any intellectual property. winbond customers using or selling these products for use in su ch applications do so at their own risk and agree to fully indemnify winbond for any damages resulting from such improper use or sales. winbond products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for surgical implantation, atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, or fo r other applications intended to support or sustain life. furthermore, winbond products are not intended fo r applications wherein failure of winbond products could result or lead to a situation wherein personal injury, deat h or severe property or environmental damage could occur.

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